Design and Implementation of an LMS-Based Speech Enhancement System on a Xilinx Zynq-7000 SoC

Abstract

Speech enhancement is essential for improving speech quality in real-time communication and embedded audio systems. This paper presents the design and implementation of an LMS-based speech enhancement system on a Xilinx Zynq-7000 System-on-Chip (SoC) using a model-based design approach. The LMS adaptive filter was developed and validated in MATLAB/Simulink using floating-point arithmetic and subsequently optimized using fixed-point representation for efficient FPGA implementation. Verilog HDL was automatically generated using MATLAB HDL Coder and deployed on the Zynq-7000 SoC through the HDL Workflow Advisor. The implemented system was evaluated using Signal-to-Noise Ratio (SNR), Mean Square Error (MSE), Short-Time Objective Intelligibility (STOI), and FPGA implementation metrics including resource utilization, timing, and power consumption. Experimental results demonstrate successful hardware implementation while preserving speech quality. The proposed workflow provides an efficient transition from algorithm development to FPGA-based speech enhancement systems.

Introduction

This paper presents a MATLAB/Simulink-based implementation of an LMS (Least Mean Square) adaptive speech enhancement system on the Xilinx Zynq-7000 System-on-Chip (SoC). The goal is to improve speech quality in noisy environments while demonstrating a complete model-based design workflow, from algorithm development to FPGA hardware implementation.

Background

Speech enhancement is widely used in mobile communication, hearing aids, teleconferencing, healthcare, and voice-controlled systems. Background noise reduces speech intelligibility and degrades system performance. The LMS adaptive filter is a popular solution because it offers:

• Low computational complexity,
• Low memory requirements,
• Stable and reliable convergence.

Unlike previous studies that focus only on algorithm implementation or hardware realization, this work integrates algorithm validation, fixed-point optimization, automatic HDL generation, hardware deployment, and implementation analysis into a single workflow.

Proposed Methodology

The system follows a model-based design approach using MATLAB/Simulink:

1. A clean speech signal is corrupted with Additive White Gaussian Noise (AWGN).
2. A correlated reference noise signal is supplied to the LMS adaptive filter.
3. The algorithm is verified using floating-point arithmetic.
4. The design is converted to fixed-point representation.
5. MATLAB HDL Coder automatically generates Verilog HDL.
6. The design is synthesized in Xilinx Vivado and deployed on a ZedBoard (Xilinx Zynq-7000 SoC).

LMS Adaptive Filter

The LMS algorithm continuously updates filter coefficients to minimize the error between the desired speech signal and the filter output. The adaptive filter estimates and removes correlated noise, producing an enhanced speech signal suitable for further analysis.

Hardware Implementation

The generated LMS filter was integrated into the Programmable Logic (PL) of the Zynq-7000 SoC, while the ARM Processing System (PS) handled control operations via an AXI4-Lite interface.

FPGA Resource Utilization

• Slice LUTs: 2,707 (5.09%)
• Slice Registers: 2,233 (2.10%)
• DSP48 Slices: 68 (30.91%)
• Slice Resources: 1,310 (9.85%)
• On-chip Power: 1.773 W
• Worst Negative Slack: +19.77 ns (successful timing closure)

These results demonstrate an efficient FPGA implementation with low hardware resource usage and acceptable power consumption.

Experimental Evaluation

The system was evaluated using:

• Floating-point simulation,
• Fixed-point simulation,
• Hardware implementation on the ZedBoard.

Performance metrics included:

• Signal-to-Noise Ratio (SNR)
• Mean Square Error (MSE)
• Short-Time Objective Intelligibility (STOI)
• Convergence behaviour
• FPGA resource utilization and timing

Results

Floating-Point Simulation

• SNR: 13.71 dB
• MSE: 1.84 × 10??
• STOI: 0.9832

Fixed-Point Simulation

• SNR: 13.71 dB
• MSE: 1.84 × 10??
• STOI: 0.9832

The fixed-point implementation closely matched the floating-point results, indicating negligible loss of accuracy.

Hardware (SoC) Implementation

• SNR: −3.96 dB
• MSE: 0.01077
• STOI: 0.6074

Although the hardware implementation successfully performed real-time speech enhancement, its speech quality was lower than the simulation results due to practical FPGA implementation constraints.

Conclusion

This paper presented the design and implementation of an LMS-based speech enhancement system on a Xilinx Zynq-7000 SoC using a model-based design approach. The proposed workflow integrated algorithm development, fixed-point optimization, automatic HDL generation, and FPGA deployment within the MATLAB/Simulink environment. Experimental results demonstrated effective speech enhancement, successful hardware implementation, and efficient FPGA resource utilization. The proposed methodology provides a practical framework for implementing adaptive signal processing algorithms on FPGA-based embedded systems. Future work will focus on real-time microphone input, advanced adaptive algorithms such as NLMS and RLS, and further optimization of hardware performance.

References

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Copyright

Copyright © 2026 Nellikonda Geethanjali, Dr. M. Madhavi Latha. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.